Semiconductor devices, such as transistors, are the core building block of the vast majority of electronic devices. In practice, it is desirable to accurately and precisely fabricate transistors and other semiconductor devices with physical features having specific physical dimensions to thereby achieve semiconductor devices having their intended performance characteristics and to improve yield. However, the hardware tools used to fabricate the devices may exhibit performance variations. As a result, devices may be fabricated with features that deviate from their specified physical dimensions, which, in turn, could lead to failures at wafer test and, accordingly, reduce yield. Thus, it is desirable to measure physical features, critical dimensions and/or other properties of devices during fabrication to correct any deviations from the intended physical dimensions and thereby reduce the likelihood of failures at wafer test and improve yield.
Obtaining highly accurate measurements using non-destructive metrologies (which reduce yield) typically take an undesirably long amount of time or undesirably increases costs. For example, to use scatterometry to measure a particular device feature of a semiconductor device structure, a specific model must be developed to convert raw measurement spectra to a corresponding measurement for that feature. The model is often developed after the process for fabricating that semiconductor device structure has been substantially established or fixed, and therefore, the time required to develop and accurate model and the time required to develop the fabrication process are compounded, thereby increasing the overall time-to-solution. Additionally, the resulting model often assumes that one or more design parameters for the semiconductor device structure are fixed (by virtue of the design process being pre-established), and therefore, is inflexible and unable to accommodate subsequent changes to those design parameters.